VLSI Design Engineer
Retym
- Where
- Ramat Gan, Israel, hybrid
- Language, from the listing
- No Hebrew mentionedA missing mention doesn't mean Hebrew isn't needed. Ask if it matters to you.
- Dates
- Found 7 Oct 2026
- Last checked on the employer's site
- 4 h ago (7 Oct 2026)
- Source
- Employer career page (Comeet)
The full listing
Description
We are looking for talented and experienced VLIS Design Engineers/Micro-architects.
As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.
In this position you will be responsible for coming up with creative solutions to architectural challenges and crafting the very fine details of the implementation
Requirements
Job requirements:
• 5 years of experience as ASIC/FPGA designer
• Strong Verilog/System-Verilog experience
• Familiar with simulation tools/environments, verification methodologies
• Strong team player, solid interpersonal skills
• Entrepreneurial can-do attitude, self-motivated, able to work independently
• BS/MS in EE/CE from lead universities
Background in one or more of the following domains is an advantage:
• Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
• Design DSP of oriented blocks
• Ethernet (100G and above)
• Scripting experience using several of the following: Python, Perl, TCL