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Verification Engineer

abra R&D

Where
Israel, on-site
Language, from the listing
No Hebrew mentioned. Mentions EnglishA missing mention doesn't mean Hebrew isn't needed. Ask if it matters to you.
Dates
Found 27 Sept 2026
Last checked on the employer's site
1 h ago (6 Oct 2026)
Source
Employer career page (Comeet)

What they ask for

  • 3+ years of experience in Verification, from Test Plan definition through Coverage - mandatory.
  • Hands-on experience with UVM methodology and SystemVerilog - mandatory.
  • Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels - mandatory.
  • Experience with RTL debugging from block level to system level - mandatory.
  • Experience writing scripts in Python, TCL, Bash / Csh - mandatory.
  • Experience working in a Linux environment - mandatory.
  • Experience working with FPGA, architecture, system, and algorithm teams.
  • Very good technical English.

Nice to have

  • B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science - an advantage.
  • Experience working with simulation tools; Questa Simulator is an advantage

The full listing

Description abra R&D is seeking a Verification Engineer. We are looking for a skilled Verification Engineer to join a professional and dynamic team and take part in advanced, diverse technology projects in the fields of FPGA Verification, signal processing, controllers, and more. This role requires extensive experience in Verification, UVM methodology, SystemVerilog, FPGA / ASIC verification environments, RTL debugging, simulation tools, scripting, and working closely with FPGA development, system, architecture, and algorithm teams. Key Responsibilities: • Develop verification environments using UVM methodology for FPGA verification across various projects. • Work on verification projects involving signal processing, controllers, and additional advanced technologies. • Define, architect, and develop verification environments from block-level to full-chip level. • Work closely with FPGA development teams, system engineers, architecture teams, and algorithm engineers. • Support RTL debugging from block level to system level. Requirements • B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science - an advantage. • 3+ years of experience in Verification, from Test Plan definition through Coverage - mandatory. • Hands-on experience with UVM methodology and SystemVerilog - mandatory. • Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels - mandatory. • Experience with RTL debugging from block level to system level - mandatory. • Experience working with simulation tools; Questa Simulator is an advantage • Experience writing scripts in Python, TCL, Bash / Csh - mandatory. • Experience working in a Linux environment - mandatory. • Experience working with FPGA, architecture, system, and algorithm teams. • Very good technical English. Personality requirements: • Strong analytical and problem-solving skills. • Ability to work independently and as part of a team. • Ability to work in a multidisciplinary environment. A full-time on-site position based in Holon, Israel.